Logic Synthesis

In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL), is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog. Some tools can generate bitstreams for programmable logic devices such as PALs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.

Read more about Logic Synthesis:  History of Logic Synthesis, Logic Elements, High-level Synthesis or Behavioral Synthesis, Multi-level Logic Minimization

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