The method of logical effort, a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit. Used properly, it can aid in selection of gates for a given function (including the number of stages necessary) and sizing gates to achieve the minimum delay possible for a circuit.
Read more about Logical Effort: Derivation of Delay in A Logic Gate, Procedure For Calculating The Logical Effort of A Single Stage, Multistage Logic Networks
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