Memory Refresh - Refresh Interval

Refresh Interval

The maximum time interval between refreshes is standardized by JEDEC for each DRAM technology, and is specified in the manufacturer's chip specifications. It is usually in the range of milliseconds. For current (2012) DDR2 SDRAM chips it is 64 ms. It depends on the ratio of charge stored in the memory cell capacitors to leakage currents. Despite the fact that the geometry of the capacitors has been shrinking with each new generation of memory chips, refresh times for DRAM have been improving; from 8 ms for 1M chips, 32 ms for 16M chips, to 64 ms for 256M chips. Longer refresh time means a smaller fraction of the device's time is occupied with refresh, leaving more time for memory accesses. Although refresh overhead occupied up to 10% of chip time in earlier DRAMs, in modern chips this fraction is less than 1%. Because the leakage currents in semiconductors increase with temperature, refresh times must be decreased at high temperature. The current generation of DDR2 SDRAM chips has a temperature-compensated refresh structure; refresh cycle time must be halved when chip case temperature exceeds 85°C (185°F).

The actual persistence of readable charge values and thus data in most DRAM memory cells is much longer than the refresh time, up to 1-10 seconds. However transistor leakage currents vary widely between different memory cells on the same chip. In order to make sure that all the memory cells are refreshed before a single bit is lost, manufacturers must set their refresh times conservatively short.