Static Power Consumption
Depletion-load circuits consume less power than enhancement-load circuits at the same speed. In both cases the connection to 1 is always active, even when the connection to 0 is also active. This results in high static power consumption. The amount of waste depends on the strength, or physical size, of the pull-up. Both normal (enhancement-mode) and depletion-mode pull-up transistors use greatest power when the output is stable at 0, so this loss is considerable. The sizes of the pull-ups are thus adjusted so that the 0 to 1 transition speed matches the 1 to 0 speed, but no more, as that would waste power. Because the strength of a depletion-mode transistor falls off less on the approach to 1, they may reach 1 faster despite starting slower, i.e. conducting less current at the beginning of the transition and at steady state.
Read more about this topic: Depletion-load NMOS Logic
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