Depletion-load NMOS Logic

Depletion-load NMOS Logic

Depletion-load nMOS/NMOS (n-channel metal-oxide-semiconductor) is a form of nMOS logic family which uses depletion-mode n-type MOSFETs as load transistors as a method to enable single voltage operation and achieve greater speed than possible with pure enhancement-load devices. This is partly because the depletion-mode MOSFETs can be a better current source approximation than the simpler enhancement-mode transistor can, especially when no extra voltage is available (one of the reasons early pMOS and nMOS chips demanded several voltages).

The inclusion of depletion-mode n-MOS transistors in the manufacturing process demanded additional manufacturing steps compared to the simpler enhancement-load circuits; this is because depletion-load devices are formed by increasing the amount of dopant in the load transistors channel region, in order to adjust their threshold voltage. This is normally performed using ion implantation.

Some depletion-load nMOS designs are still produced, typically in parallel with newer CMOS counterparts; one example of this is the Z84015 and Z84C15.