Bulldozer (microarchitecture) - Basic Description

Basic Description

According to AMD, Bulldozer-based CPUs are based on GlobalFoundries's 32 nm Silicon on insulator (SOI) process technology and reuses the approach of DEC for multitask computer performance with the arguments of, according to press notes, "balances dedicated and shared computer resources to provide a highly compact, high units count design that is easily replicated on a chip for performance scaling." In other words, by eliminating some of the "redundant" elements that naturally creep into multicore designs, AMD has hoped to take better advantage of its hardware capabilities, while using less power.

Bulldozer-based implementations built on 32nm SOI with HKMG arrived in October 2011 for both servers and desktops. The server segment included the dual chip (16-threads) Opteron processor codenamed Interlagos (for Socket G34) and single chip (4, 6 or 8 threads) Valencia (for Socket C32), while the Zambezi (4, 6 and 8 threads) targeted desktops on Socket AM3+.

Bulldozer is the first major redesign of AMD’s processor architecture since 2003, when the firm launched its K8 processors, and also features two 128-bit FMA-capable FPUs which can be combined into one 256-bit FPU. This design is accompanied by two integer clusters, each with 4 pipelines (the fetch/decode stage is shared). Bulldozer will also introduce shared L2 cache in the new architecture. AMD's marketing service calls this design a "Module". A 16-threads processor design would feature eight of these "modules", but the operating system will recognize each "module" as two logical cores.

The "module", described as two logical cores, can be contrasted with a single Intel core with HyperThreading. The only difference between the two approaches is that Bulldozer provides dedicated schedulers and integer units for each thread, whereas in Intel's core all threads must compete for available execution resources.