XDR DRAM - Protocol

Protocol

An XDR RAM chip's high-speed signals are a differential clock input (clock from master, CFM/CFMN), a 12-bit single-ended request/command bus (RQ11..0), and a bidirectional differential data bus up to 16 bits wide (DQ15..0/DQN15..0). The request bus may be connected to several memory chips in parallel, but the data bus is point to point; only one RAM chip may be connected to it. To support different amounts of memory with a fixed-width memory controller, the chips have a programmable interface width. A 32-bit-wide DRAM controller may support 2 16-bit chips, or be connected to 4 memory chips each of which supplies 8 bits of data, or up to 16 chips configured with 2-bit interfaces.

In addition, each chip has a low-speed serial bus used to determine its capabilities and configure its interface. This consists of three shared inputs: a reset line (RST), a serial command input (CMD) and a serial clock (SCK), and serial data in/out lines (SDI and SDO) that are daisy-chained together and eventually connect to a single pin on the memory controller.

All single-ended lines are active-low; an asserted signal or logical 1 is represented by a low voltage.

The request bus operates at double data rate relative to the clock input. Two consecutive 12-bit transfers (beginning with the falling edge of CFM) make a 24-bit command packet.

The data bus operates at 8x the speed of the clock; a 400 MHz clock generates 3200 MT/s. All data reads and writes operate in 16-transfer bursts lasting 2 clock cycles.

Request packet formats are as follows:

XDR DRAM request packet formats
Clock edge	Bit	Bit	Bit	Description	Bit	Description	Bit	Description	Bit	Description	Bit	Description
Clock edge	Bit	NOP	Column read/write		Calibrate/power-down		Precharge/refresh		Row Activate		Masked write
↓	RQ11	0	0	COL opcode	0	COLX opcode	0	ROWP opcode	0	ROWA opcode	1	COLM opcode
↓	RQ10	0	0		0		0		1	ROWA opcode	M3	Write mask low bits
↓	RQ9	0	0		1		1		R9	Row address high bits	M2
↓	RQ8	0	1		0		1		R10		M1
↓	RQ7	x	WRX	Write/Read bit	x	reserved	POP1	Precharge delay (0..3)	R11		M0
↓	RQ6	x	C8	Column address high bits	x		POP0	Precharge delay (0..3)	R12	reserved	C8	Column address high bits
↓	RQ5	x	C9	Column address high bits	x		x	reserved	R13		C9	Column address high bits
↓	RQ4	x	C10	reserved	x		x		R14		C10	reserved
↓	RQ3	x	C11	reserved	XOP3	Subopcode	x		R15		C11	reserved
↓	RQ2	x	BC2	Bank address	XOP2		BP2	Precharge bank	BA2	Bank address	BC2	Bank address
↓	RQ1	x	BC1		XOP1		BP1		BA1		BC1
↓	RQ0	x	BC0		XOP0		BP0		BA0		BC0
↑	RQ11	x	DELC	Command delay (0..1)	x	reserved	POP2	Precharge enable	DELA	Command delay (0..1)	M7	Write mask high bits
↑	RQ10	x	x	reserved	x		ROP2	Refresh command	R8	Row address low bits	M6
↑	RQ9	x	x		x		ROP1		R7		M5
↑	RQ8	x	x		x		ROP0		R6		M4
↑	RQ7	x	C7	Column address low bits	x		DELR1	Refresh delay (0..3)	R5		C7	Column address low bits
↑	RQ6	x	C6		x		DELR0	Refresh delay (0..3)	R4		C6
↑	RQ5	x	C5		x		x	reserved	R3		C5
↑	RQ4	x	C4		x		x		R2		C4
↑	RQ3	x	SC3	Sub-column address	x		x		R1		SC3	Sub-column address
↑	RQ2	x	SC2		x		BR2	Refresh bank	R0		SC2
↑	RQ1	x	SC1		x		BR1		SR1	Sub-row address	SC1
↑	RQ0	x	SC0		x		BR0		SR0	Sub-row address	SC0

There are a large number of timing constraints giving minimum times that must elapse between various commands (see Dynamic random-access memory: Memory timing); the DRAM controller sending them must ensure they are all met.

Some commands contain delay fields. These delay the effect of the command by the given number of clock cycles. This permits multiple commands (to different banks) to take effect on the same clock cycle.