Introduction and Features
The W65C02S is the Western Design Center's version of the 65C02 microprocessor. The "S" designation indicates that the part has a fully static core which allows the primary (Ø2) clock to be slowed down or fully stopped in either the high or low state with no loss of data. Typical microprocessors not implemented in CMOS have dynamic cores and will lose their internal register contents (and thus crash) if they are not continuously clocked at a rate between some minimum and maximum specified values.
The W65C02S is a low-power general-purpose 8-bit microprocessor (8-bit registers and data bus) with a 16-bit program counter and address bus. The variable length instruction set and manually optimized core size are intended to make the W65C02S well suited for low power system-on-chip (SoC) designs.
WDC makes a Verilog hardware description model available for designing the 65C02 core into ASICs and FPGAs. As is common in the semiconductor industry, the company also provides a development system, which includes a developer board, an in-circuit emulator (ICE) and a software development system.
Read more about this topic: WDC 65C02
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