General Improvements To Classical Verilog
In addition to the new features above, SystemVerilog enhances the usability of Verilog's existing language features. The following are some of these enhancements:
- The procedural assignment operator(s) (<=, =) can now operate directly on arrays.
- Port (inout, input, output) definitions are now expanded to support a wider variety of datatypes: struct, enum, real, and multi-dimensional types are supported.
- The for-loop construct now allows automatic variable declaration inside the for statement. And loop-control is improved by the continue and break statements.
- SystemVerilog adds a do/while to the while construct.
- Constant variables, i.e. those designated as non-changing during runtime, can be designated by use of const.
- Variable initialization can now operate on arrays.
- The preprocessor has improved `define macro-substitution capabilities, specifically substitution within literal-strings (""), as well as concatenation of multiple macro-tokens into a single word.
- The fork/join construct has been expanded with join_none and join_any.
- Additions to the `timescale directive allow simulation timescale to be controlled more predictably in a large simulation environment, with each source-file using a local timescale.
- Task ports can now be declared ref. A reference gives the task body direct access to the source arguments. in the caller's scope. Since it is operating on the original variable itself, rather than a copy of the argument's value, the task/function can modify variables (but not nets) in the caller's scope in realtime. The inout/output port-declarations pass variables by value, and defer updating the caller-scope variable until the moment the task exits.
- Functions can now be declared void, which means it returns no value.
- Parameters can be declared any type, including user-defined typedefs.
Besides this, SystemVerilog allows convenient interface to foreign languages (like C/C++), by SystemVerilog DPI (Direct Programming Interface).
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