Q-Bus - Main Features of The Q-bus

Main Features of The Q-bus

Like the Unibus before it, the Q-bus used:

• Memory-mapped I/O
• Byte addressing
• A strict master-slave relationship between devices on the bus
• Asynchronous signaling

Memory-mapped I/O means that data cycles between any two devices, whether CPU, memory, or I/O devices, used the same protocols. On the Unibus, a range of physical addresses were dedicated for I/O devices. The Q-bus simplified this design by providing a specific signal (originally called BBS7, Bus Bank Select 7 but later generalized to be called BBSIO, Bus Bank Select I/O) that selected the range of addresses used by the I/O devices.

Byte addressing means that the physical address passed on the Unibus was interpreted as the address of a byte-sized quantity of data. Because the bus actually contained a data path that was two bytes wide, address bit was subject to special interpretation and data on the bus had to travel in the correct byte lanes.

A strict Master-Slave relationship means that at any point in time, only one device could be the Master of the Q-bus. This master device could initiate data transactions which could then be responded to by a maximum of one selected slave device. (This had no effect on whether a given bus cycle was reading or writing data; the bus master could command either type of transaction.) At the end of the bus cycle, a bus arbitration protocol would then select the next device to be given mastership of the bus.

Asynchronous signaling means that the bus had no fixed cycle time; the duration of any particular data transfer cycle on the bus was determined solely by the master and slave devices participating in the current data cycle. These devices used handshake signals to control the timing of the data cycle. Timeout logic within the master device limited the maximum allowed length of any given bus cycle.

Depending on its generation, the Q-bus contained 16, 18, or 22 BDAL (Bus Data/Address Line) lines. 16, 18, or 22 BDAL lines were used for the physical address portion of each bus cycle. Eight or 16 DBAL lines were then re-used for the data portion(s) of each bus cycle. Newer generations of the bus allowed block mode transfer where a single bus address could be followed by more than one data cycle (with the transfers taking place at consecutive bus addresses). Because the address portion of each bus cycle can not transfer data, the use of block mode meant fewer address cycles and more time for data cycles, allowing increased bus data transfer bandwidth.

Bus mastery was awarded based on an I/O card's geographical proximity to the bus arbitrator (at the logical front of the bus); closer cards were granted priority over further cards.

Interrupts could be delivered to the Interrupt Fielding Processor at any of four priority levels. Within a given level, the cards closer to the IFP (at the front of the bus) took priority over cards further back on the bus. Interrupts were vectored: a card requesting an interrupt had its interrupt vector read by the IFP. In this way, the interrupts from all I/O cards in the system could be distinguished with no ambiguity.