NEC SX Architecture - SX Series Systems

SX Series Systems

Since the SX-4, SX series supercomputers are constructed in a doubly parallel manner. A number of central processing units (CPUs) are arranged into a parallel vector processing node. These nodes are then installed in a regular SMP arrangement.

Single node SX systems
SX-2 SX-3 SX-4 SX-5 SX-6 SX-7 SX-8 SX-8R SX-9
Max. CPUs 1 4 32 16 8 32 8 8 16
Peak CPU GFLOPS 1.3 5.5 2 8 8 8.83 16 35.2 102.4
Peak system GFLOPS 1.3 22 64 128 64 282 128 281.6 1638
Max. main memory 256 MB 2 GB 16 GB 128 GB 64 GB 256 GB 128 GB 256 GB 1 TB
System memory B/W (GB/s) 11 44 512 1,024 256 1,129 512 563.2 4,096
Memory B/W per CPU (GB/s) 11 22 16 64 32 35.3 64 70.4 256
Multi-node SX systems
SX-4 SX-4A SX-5 SX-6 SX-8 SX-8R SX-9
Max. nodes 16 16 32 128 512 512 512
Max. CPUs 512 256 512 1,024 4,096 4,096 8,192
Peak TFLOPS 1 0.5 4 8 65 140.8 839
Max. main memory 256 GB 512 GB 4 TB 8 TB 64 TB 128 TB 512 TB
Total memory B/W (TB/s) 8 4 32 32 131 281.6 2,048

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