The LC-3b
The LC-3b ISA describes a modified version of the LC-3 that includes the following changes:
- The machine's word size remains 16 bits, but its memory is now byte-addressable with the same address space.
- The LD and ST instructions (load and store data using PC-relative addressing) have been removed.
- The LDI and STI instructions (indirect loads and stores) use register-based addressing instead of PC-relative addressing.
- Two instructions, LDB and STB, have been added to manipulate individual bytes of memory; the other load and store instructions continue to act on entire words.
- The reserved opcode has been converted into a shift instruction, SHF, that supports arithmetic and logical shifts of arbitrary size in both directions.
These changes make the hardware of the LC-3b slightly more complex than that of the LC-3. For example, the LC-3b needs a shifter (the LC-3 does not) and extra logic in its memory unit to properly handle loading and storing data of various sizes.
Ashley Wise maintains a set of tools for simulating and working with the LC-3b.
Read more about this topic: LC-3