Physical Implementation
The 8080 integrated circuit used non-saturated enhancement load nMOS gates, demanding extra voltages (for the load-gate bias). It was manufactured in a silicon gate process using a minimum feature size of 6 µm. A single layer of metal was used to interconnect the approximately 6,000 transistors in the design, but the higher resistance polysilicon layer, which required higher voltage for some interconnects, was implemented with transistor gates. The die size was approximately 20 mm².
Read more about this topic: Intel 8080
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