HP 3000 - Use of Stack Instead of Registers

Use of Stack Instead of Registers

Most current computer instruction sets are based on a general purpose register model. The processor and memory architecture of the classic HP 3000 were based on a stack machine model, like HP's well-known line of RPN calculators. It was said to be inspired by the famous stack-based Burroughs large systems. Rather than having a small number of registers, for example only an AX and BX register in the case of the HP 1000, operands would be pushed on the same stack used to store local variables and return addresses. So rather than

you would have

The 16-bit microcoded machines (Series I, II, III, 30, 33, 39, 40, 42, 44, 48, 52, 58, 64, 68, 70, 37, ...) implement a 16-bit word addressed, byte-addressable, segmented, Harvard, Stack Instruction Set Architecture (ISA). Most of the ~214 instructions are 16 bits wide. Stack operations pack 2 per 16-bit word and the remaining few are 32 bits wide.

CISC Implementations

• III: 4 Top of stack registers, 175 ns microinstruction cycle time → 5.7 MHz
• 30, 33: Silicon on sapphire, 2 Top of stack registers, 90 ns microinstruction cycle time → 11 MHz, instructions take 3-7 cycles
• 40, 42, 44, 48: Schottky TTL, 4 Top of stack registers, 105 ns microinstruction cycle time → 9.5 MHz
• 64, 68: ECL, 8 Top of Stack registers, 75 ns microinstruction cycle time → 13 MHz, 8KB cache, 60KB WCS, 2 16-bit ALUs
• 37: ~8,000-gate CMOS gate array, 4 Top of Stack registers

Later 32-bit models used HP's PA-RISC general register-based RISC architecture.

PA-RISC Implementations

• PA-RISC 1.0 Series 925, 930, 935, 949, 950, 955, 960, 980
• PA-RISC 1.1 Series 917, 920, 922, 927, 937, 947, 948, 957, 958, 967, 977sx, 987, 990, 991, 992, 995, 918, 928, 968, 978, 988
• PA-RISC 2.0 Series 996, A and N class and the 9x9 series