Design Closure - Reference ASIC Design Flow

Reference ASIC Design Flow

• Concept phase: Functional objectives and architecture of a chip are developed.
• Logic design: Architecture is implemented in a register transfer level (RTL) language, then simulated to verify that it performs the desired functions. This includes functional verification.
• Floorplanning: The RTL of the chip is assigned to gross regions of the chip, input/output (I/O) pins are assigned and large objects (arrays, cores, etc.) are placed.
• Logic synthesis: The RTL is mapped into a gate-level netlist in the target technology of the chip.
• Design for Testability: The test structures like scan chains are inserted.
• Placement: The gates in the netlist are assigned to nonoverlapping locations on the chip.
• Logic/placement refinement: Iterative logical and placement transformations to close performance and power constraints.
• Clock insertion: Balanced buffered clock trees are introduced into the design.
• Routing: The wires that connect the gates in the netlist are added.
• Postwiring optimization: Remaining performance, noise, and yield violations are removed.
• Design for manufacturability: The design is modified, where possible, to make it as easy as possible to produce.
• Signoff checks: Since errors are expensive, time consuming and hard to spot, extensive error checking is the rule, making sure the mapping to logic was done correctly, and checking that the manufacturing rules were followed faithfully.
• Tapeout and mask generation: the design data is turned into photomasks in mask data preparation.