Evolution From Preceding NMOS Types
Depletion-load processes differ from their predecessors in the way the Vdd voltage source, representing 1, connects to each gate. In both technologies, each gate contains one NMOS transistor which is permanently turned on and connected to Vdd. When the transistors connecting to 0 turn off, this pull-up transistor determines the output to be 1 by default. In standard NMOS, the pull-up is the same kind of transistor as is used for logic switches. As the output voltage approaches a value less than Vdd, it gradually switches itself off. This slows the 0 to 1 transition, resulting in a slower circuit. Depletion-load processes replace this transistor with a depletion-mode NMOS at a constant gate bias, with the gate tied directly to the source. This alternative type of transistor acts as a current source until the output approaches 1, then acts as a resistor. The result is a faster 0 to 1 transition.
Read more about this topic: Depletion-load NMOS Logic
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