Depletion-load NMOS Logic - Compared To CMOS

Compared To CMOS

Compared to static CMOS, all variants of nMOS (and pMOS) are relatively power hungry. This is because they rely on load-transistors working as resistors in steady state, where the quiescent current determines the maximum possible load at the output as well as the speed of the gate (i.e. with other factors constant). This contrasts to the power consumption characteristics of static CMOS circuits, which is due only to the transient power draw when the output state is changed and the p- and n-transistors thereby briefly conduct at the same time. However, this is a simplified view, and a more complete picture has to also include the fact that even purely static CMOS circuits have significant leakage in modern tiny geometries, as well as the fact that modern CMOS chips often contain dynamic and/or domino logic with a certain amount of pseudo nMOS circuitry.