Operators
Note: These operators are not shown in order of precedence.
| Operator type | Operator symbols | Operation performed |
|---|---|---|
| Bitwise | ~ | Bitwise NOT (1's complement) |
| & | Bitwise AND | |
| | | Bitwise OR | |
| ^ | Bitwise XOR | |
| ~^ or ^~ | Bitwise XNOR | |
| Logical | ! | NOT |
| && | AND | |
| || | OR | |
| Reduction | & | Reduction AND |
| ~& | Reduction NAND | |
| | | Reduction OR | |
| ~| | Reduction NOR | |
| ^ | Reduction XOR | |
| ~^ or ^~ | Reduction XNOR | |
| Arithmetic | + | Addition |
| - | Subtraction | |
| - | 2's complement | |
| * | Multiplication | |
| / | Division | |
| ** | Exponentiation (*Verilog-2001) | |
| Relational | > | Greater than |
| < | Less than | |
| >= | Greater than or equal to | |
| <= | Less than or equal to | |
| == | Logical equality (bit-value 1'bX is removed from comparison) | |
| != | Logical inequality (bit-value 1'bX is removed from comparison) | |
| === | 4-state logical equality (bit-value 1'bX is taken as literal) | |
| !== | 4-state logical inequality (bit-value 1'bX is taken as literal) | |
| Shift | >> | Logical right shift |
| << | Logical left shift | |
| >>> | Arithmetic right shift (*Verilog-2001) | |
| <<< | Arithmetic left shift (*Verilog-2001) | |
| Concatenation | {, } | Concatenation |
| Replication | {n{m}} | Replicate value m for n times |
| Conditional | ? : | Conditional |
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