Transmeta - Technology

Technology

The actual Transmeta processors are in-order very long instruction word (VLIW) cores. To execute x86 code, a pure software-based instruction translator dynamically compiles or emulates x86 code sequences, using execution-hotspot guided heuristics. While similar technologies existed (Wabi for Solaris and Linux, FX!32 for Alpha and IA-32 EL for Itanium, open-source DAISY, the Mac 68K emulator for the PowerPC) in the 1990s, the Transmeta approach has set a much higher bar for compatibility—able to execute all x86 instructions from initial boot up to the latest multimedia instructions—while retaining most of its core performance.

Transmeta trademarked the term "code-morphing" to describe their technology.

The operation of Transmeta's code-morphing systems software is very similar to the final optimisation pass of a conventional compiler. Considering a fragment of 32-bit x86 code:

addl %eax,(%esp) // load data from stack, add to %eax addl %ebx,(%esp) // ditto, for %ebx movl %esi,(%ebp) // load %esi from memory subl %ecx,5 // subtract 5 from %ecx register

This is first converted simplistically into native instructions:

ld %r30, // load from stack, into temporary add.c %eax,%eax,%r30 // add to %eax, set condition codes. ld %r31, add.c %ebx,%ebx,%r31 ld %esi, sub.c %ecx,%ecx,5

The optimiser then eliminates common subexpressions and unnecessary condition code operations and, potentially, applies other optimisations such as loop unrolling:

ld %r30, // load from stack only once add %eax,%eax,%r30 add %ebx,%ebx,%r30 // reuse data loaded earlier ld %esi, sub.c %ecx,%ecx,5 // only this last condition code needed

Finally, the optimiser groups individual instructions ("atoms") into VLIW opcodes ("molecules") for the underlying hardware:

ld %r30,; sub.c %ecx,%ecx,5 ld %esi,; add %eax,%eax,%r30; add %ebx,%ebx,%r30

These two VLIW opcodes will be executed in two clock cycles, as opposed to the larger number required for the original code executed on an x86 processor which did not perform complex optimisations in hardware.

Transmeta claims several technical benefits to this approach:

1. As the market leaders Intel and/or AMD would extend the core x86 instruction set, Transmeta could quickly upgrade their product with a software upgrade rather than requiring a respin of their hardware. This method just emphasises the compatibility rather than the performance.
2. Performance and power can be tuned in software to meet market needs.
3. It would be relatively simple to fix hardware design or manufacturing flaws in the hardware using software workarounds.
4. More time could be spent concentrating on enhancing the capabilities of the core or reducing its power consumption without worrying about 33 years of backward compatibility to the x86 architecture.
5. The processor could emulate multiple other architectures, possibly even at the same time. (At its initial Crusoe launch, Transmeta demonstrated pico-Java and x86 running intermixed on the native hardware.)

Prior to Crusoe's release, rumors indicated Transmeta was relying on these benefits to develop a hybrid PowerPC and x86 processor. But Transmeta would initially concentrate solely on the extremely low-power x86 market.

The ability to quickly update products without a hardware respin was demonstrated in 2002 with an in-the-field upgrade (a download) to enhance CPU performance of the Crusoe based HP Compaq TC1000 tablet PC. It was used again in 2004 when NX bit and SSE3 support were added to the Efficeon product line without requiring hardware changes. In the field upgrades were rare in practice due to system hardware vendors not wanting to incur additional customer support costs or spend additional money on QA for the potential upgrades or bug fixes to shipped products they had already closed the revenue books on.