In CPU design, a Sum Addressed Decoder or Sum Addressed Memory (SAM) Decoder is a method of reducing the latency of the CPU cache access. This is achieved by fusing the address generation sum operation with the decode operation in the cache SRAM.
Read more about Sum Addressed Decoder: Overview, Sum-addressed Cache: Collapse The Adder and Decoder, Ignoring The LSBs: Late Select On Carry, Match Generation, Gate Level Implementation, What Has Been Saved?, Further Optimizations: Predecode
Famous quotes containing the words sum and/or addressed:
“To die proudly when it is no longer possible to live proudly. Death freely chosen, death at the right time, brightly and cheerfully accomplished amid children and witnesses: then a real farewell is still possible, as the one who is taking leave is still there; also a real estimate of what one has wished, drawing the sum of one’s life—all in opposition to the wretched and revolting comedy that Christianity has made of the hour of death.”
—Friedrich Nietzsche (1844–1900)
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—Beatrice Curtis Brown (1901–1974)