In CPU design, a Sum Addressed Decoder or Sum Addressed Memory (SAM) Decoder is a method of reducing the latency of the CPU cache access. This is achieved by fusing the address generation sum operation with the decode operation in the cache SRAM.
Read more about Sum Addressed Decoder: Overview, Sum-addressed Cache: Collapse The Adder and Decoder, Ignoring The LSBs: Late Select On Carry, Match Generation, Gate Level Implementation, What Has Been Saved?, Further Optimizations: Predecode
Other articles related to "sum addressed decoder, decoder":
... Many decoder designs avoid high-Fan-In AND gates in the decode line itself by employing a predecode stage ... For instance, an 11 bit decoder might be predecoded into three groups of 4, 4, and 3 bits each ... The decoder line then becomes a 3 input AND gate ...
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