Sum Addressed Decoder - Sum-addressed Cache: Collapse The Adder and Decoder

Sum-addressed Cache: Collapse The Adder and Decoder

The SRAM decoder for this example has an 11 bit input, Addr, and 2048 outputs, the decoded word lines. One word line is driven high in response to each unique Addr value.

In the simplest form of decoder, each of the 2048 lines is logically an AND gate. The 11 bits (call them A and their complements (call them B) are driven up the decoder. For each line, 11 bits or complements are fed into an 11-input AND gate. For instance, 1026 decimal is equal to 10000000010 binary. The function for line 1026 would be:

wordline = A & B & B & B & B & B & B & B & B & A & B

Both the carry chain of the adder and the decoder combine information from the entire width of the index portion of the address. Combining information across the entire width twice is redundant. A sum-addressed SRAM combines the information just once by implementing the adder and decoder together in one structure.

Recall that the SRAM is indexed with the result of an add. Call the summands R (for register) and O (for the offset to that register). The sum-addressed decoder is going to decode R+O. For each decoder line, call the line number L.

Suppose that our decoder drove both R and O over each decoder line, and each decoder line implemented:

wordline = (R+O)==L (R+O)==L <=> R+O-L==0 <=> R+O+~L+1==0 <=> R+O+~L==-1==11..1.

A set of full adders can be used to reduce R+O+~L to S+C (this is carry save addition). S+C==11..1 <=> S==~C. There will be no carries in the final add. Note that since C is a row of carries, it's shifted up one bit, so that R+O+~L == {0,S} + {C,0}

With this formulation, each row in the decoder is a set of full adders which reduce the base register, the offset, and the row number to a carry-save format, and a comparator. Most of this hardware will be proven redundant below, but for now it's simpler to think of it all existing in each row.