Sum Addressed Decoder - Gate Level Implementation

Gate Level Implementation

R₁₃ ... R₆ R₅ R₄ R₃ O₁₃ ... O₆ O₅ O₄ O₃ L₁₃ ... L₆ L₅ L₄ L₃ -------------------------- S₁₃ ... S₆ S₅ S₄ S₃ C₁₄ C₁₃ ... C₆ C₅ C₄

Before we begin collapsing redundancy between rows, let's review: Each row of each decoder for each of two banks implements a set of full adders which reduce the three numbers to be added (R, O, and L) to two numbers (S and C). The LSB (==S) is discarded. Carry out (==C) is also discarded. The row matches if S == ~C, which is &( xor(S, C)).

We can partially specialize the full adders to 2-input and, or, xor, and xnor because the L input is constant. The resulting expressions are common to all lines of the decoder and can be collected at the bottom.

S_0;i = S(R_i, O_i, 0) = R_i xor O_i S_1;i = S(R_i, O_i, 1) = R_i xnor O_i C_0;i+1 = C(R_i, O_i, 0) = R_i and O_i C_1;i+1 = C(R_i, O_i, 1) = R_i or O_i.

At each digit position, there are only two possible S_i, two possible C_i, and four possible xors between them:

L_i=0 and L_i-1=0: X_0;0;i = S_0;i xor C_0;i = R_i xor O_i xor (R_i-1 and O_i-1) L_i=0 and L_i-1=1: X_0;1;i = S_0;i xor C_1;i = R_i xor O_i xor (R_i-1 or O_i-1) L_i=1 and L_i-1=0: X_1;0;i = S_1;i xor C_0;i = R_i xnor O_i xor (R_i-1 and O_i-1) = !X_0;0;i L_i=1 and L_i-1=1: X_1;1;i = S_1;i xor C_1;i = R_i xnor O_i xor (R_i-1 or O_i-1) = !X_0;1;i

One possible decoder for our example might calculate these four expressions for each of the bits 4..13, and drive all 40 wires up the decoder. Each line of the decoder would select one of the four wires for each bit, and consist of an 10-input AND.