Standard Cell - Library

Library

A standard cell library is a collection of low-level electronic logic functions such as AND, OR, INVERT, flip-flops, latches, and buffers. These cells are realized as fixed-height, variable-width full-custom cells. The key aspect with these libraries is that they are of a fixed height, which enables them to be placed in rows, easing the process of automated digital layout. The cells are typically optimized full-custom layouts, which minimize delays and area.

A typical standard-cell library contains two main components:

  1. Library Database - Consists of a number of views often including layout, schematic, symbol, abstract, and other logical or simulation views. From this, various information may be captured in a number of formats including the Cadence LEF format, and the Synopsys Milkyway format, which contain reduced information about the cell layouts, sufficient for automated "Place and Route" tools.
  2. Timing Abstract - Generally in Liberty format, to provide functional definitions, timing, power, and noise information for each cell.

A standard-cell library may also contain the following additional components:

  • A full layout of the cells
  • Spice models of the cells
  • Verilog models or VHDL Vital models
  • Parasitic Extraction models
  • DRC rule decks

An example is a simple XOR logic gate, which can be formed from OR, INVERT and AND gates.

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