Q-Bus - Logic Minimization

Logic Minimization

As with the Unibus, the signaling was carefully optimized so that the minimum amount of logic was required across the entire bus system. Asynchronous signaling was used but all responsibility for de-skewing of addresses and data was the responsibility of the current bus master, minimizing the complexity of the bus slave devices. The responsibility for timing-out failed bus cycles also was placed in the master devices. Similarly, the complexities of handling interrupt transactions were concentrated into the single Interrupt-Fielding Processor (the PDP-11 or VAX-11 computer) in the system.