Description
The concept, proposed in 1958, pioneered Emitter-coupled logic (ECL) circuitry, pipelining, and transistor memory with a design goal of 100x speedup compared to ILLIAC I.
ILLIAC II had 8192 words of core memory, backed up by 65,536 words of storage on magnetic drums. The core memory access time was 1.8 to 2 µs. The magnetic drum access time was 7 µs. A "fast buffer" was also provided for storage of short loops and intermediate results (similar in concept to what is now called cache). The "fast buffer" access time was 0.25 µs.
The word size was 52 bits.
Floating point numbers used a format with 7 bits of exponent (power of 4) and 45 bits of mantissa.
Instructions were either 26 bits or 13 bits long, allowing packing of up to 4 instructions per memory word.
Rather than naming the pipeline stages, "Fetch, Decode, and Execute" (as on Stretch), the pipelined stages were named, "Advanced Control, Delayed Control, and Interplay".
Read more about this topic: ILLIAC II
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