Formal equivalence checking process is a part of electronic design automation (EDA), commonly used during the development of digital integrated circuits, to formally prove that two representations of a circuit design exhibit exactly the same behavior.
Read more about Formal Equivalence Checking: Equivalence Checking and Levels of Abstraction, Synchronous Machine Equivalence, Methods, Commercial Applications For Equivalence Checking, Generalizations
Famous quotes containing the word formal:
“The bed is now as public as the dinner table and governed by the same rules of formal confrontation.”
—Angela Carter (1940–1992)