Zilog Z800 - Short Description

Short Description

There was no expansion of the register set but the registers and instructions were significantly orthogonalized in order to make them more general purpose and powerful. Many new 8-bit and 16-bit operations were added, and the HL, IX, and IY registers were upgraded from their rather limited possibilities as accumulators in the Z80 to more versatile accumulators. In addition to the register operands possible in the Z80, they could be used with immediate data, direct address, register indirect, or indexed operands, even program counter-relative. Eight-bit operations had even more possibilities, including stack pointer-relative addressing and a choice of 8-bit or 16-bits immediate offsets.

The address bus was expanded to 24-bits to address 16 MB of memory. The chip was offered with either a 19-bit external bus for 512kB RAM, or a full 24-bit bus for 16MB RAM, the advantage to the smaller bus was a smaller 40-pin package. Like the Z80 before it, the Z800 retained the internal DRAM controller and clock, but added 256 bytes of RAM that could be used either as "scratchpad" RAM, or as a cache. When used in cache mode the programmer could configure it as a data or instruction cache, or both, and the internal memory controller then used it to reduce access to (slower) external memory.

There were also ambitious provisions for multiprocessing and either loosely or tightly coupled slave processors, with or without shared global memory. This was known as the extended processing architecture and extended processing units (EPU).

Another change was the addition of an optional 16-bit data bus, which doubled the rate at which it could access memory if set up properly. Combined with the two address bus sizes this meant that the chip was offered in a total of four versions: