Comparisons
Wishbone Control Signals Compared to Other SOC Bus Standards
| Wishbone | Avalon Bus | Description |
|---|---|---|
| cyc | = !write_n or !read_n | indicates that a valid bus cycle is in progress |
| stb | = chipselect | indicates a valid data transfer cycle |
| we | = !write_n and read_n | indicates whether the current local bus cycle is a READ or WRITE cycle. The signal is negated during READ cycles, and is asserted during WRITE cycles. |
| ack | = !waitrequest | indicates the termination of a normal bus cycle by slave device. |
| Avalon Bus | Wishbone | Description |
|---|---|---|
| chipselect | = stb | indicates that slave device is selected. |
| write_n | = !(cyc and we) | indicated that master requests to write to slave device. |
| read_n | = !(cyc and !we) | indicated that master requests to read from slave device. |
| waitrequest | = !ack | indicates that slave requests that master wait. |
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