WDC 65816/65802 - Features

Features

  • Fully static CMOS design for low power consumption (300 µA at 1 MHz) and increased noise immunity.
  • Wide operating voltage range: 1.8 V ± 5%, 2.5 V ± 5%, 3.0 V ± 5%, 3.3 V ± 10%, 5.0 V ± 5% for use with varying voltage peripherals.
  • Wide operating frequency range.
  • Emulation mode allows complete software compatibility with the 65C02, excepting undocumented opcodes.
  • 24-bit memory addressing provides access to 16 MB of memory space.
  • 16-bit ALU, accumulator, stack pointer and index registers.
  • Valid Data Address (VDA) and Valid Program Address (VPA) outputs for dual cache and cycle steal DMA implementation.
  • Vector Pull (VPB) output to indicate when an interrupt vector is being addressed.
  • Abort (ABORTB) input and associated vector supports processor repairs of bus error conditions, such as memory access violations.
  • Separate program and data bank registers allow program segmentation or 16 MB linear addressing (data only).
  • Direct register and stack relative addressing provides capability for reentrant, recursive and re-locatable programming.
  • 24 addressing modes—13 original 6502 modes with 92 instructions using 256 op codes, including most new opcodes implemented in the 65C02.
  • Block-move instructions, allowing rapid copying of data structures from one area of RAM to another with minimal code.
  • Wait-for-Interrupt (WAI) and Stop-the-Clock (STP) instructions further reduce power consumption, decrease interrupt latency and allows synchronization with external events.
  • Co-Processor (COP) instruction with associated vector supports co-processor configurations, e.g., floating point processors
  • Reserved "escape" (WDM) instruction for future two-byte opcodes and a link to future designs. WDM are the initials of W65C816S designer William D. Mensch.

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