VIA Nano - Features

Features

  • x86-64 instruction set
  • Superscalar out-of-order instruction execution
  • 65 nm manufacturing process
  • 40 nm manufacturing process for VIA Nano x2
  • Clock speed of 1 GHz to 2 GHz
  • Bus speed of 533 MHz or 800 MHz (1066 MHz in Nano x2)
  • Support for ECC
  • x86 virtualization (Intel-compatible implementation), deactivated before stepping 3
  • 32 KB L1 cache and 512 KB L2 cache, 64 KB L1 cache and 1 MB L2 cache (in Nano x2)
  • Pin-compatible with the VIA C7 and VIA EDEN

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