Design Choices
- C7 Esther as an evolutionary step after C3 Nehemiah, in which VIA / Centaur followed their traditional approach of balancing performance against a constrained transistor / power budget.
- The cornerstone of the C3 series chips' design philosophy has been that even a relatively simple in-order scalar core can offer reasonable performance against a complex superscalar out-of-order core if supported by an efficient "front-end", i.e. prefetch, cache and branch prediction mechanisms.
- In the case of C7, the design team have focused on further streamlining the (front-end) of the chip, i.e. cache size, associativity and throughput as well as the prefetch system. At the same time no significant changes to the execution core (back-end) of the chip.
- The C7 successfully further closes the gap in performance with AMD / Intel chips, since clock speed is not thermally constrained.
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