Pipeline Operation
Two characteristics of the ’C4x that contribute to its high performance are pipelining and concurrent I/O and CPU operation. Four functional units control ’C4x pipeline operation: fetch, decode, read, and execute. Pipelining is the overlapping or parallel operations of the fetch, decode, read, and execute levels of a basic instruction.
The four major units of the ’C4x pipeline structure and their functions are as follows:
- Fetch Unit (F)- Fetches the instruction words from memory and updates the program counter.
- Decode Unit (D)- Decodes the instruction word and performs address generation. Also, controls modification of the ARn registers in the indirect addressing mode, and of the stack pointer when PUSH to or POP from the stack occurs.
- Read Unit (R) If required, reads the operands from memory.
- Execute Unit (E) If required, reads the operands from the register file, performs the necessary operation, and writes results to the register file. If required, results of previous operations are written to memory.
Read more about this topic: TMS320C4x
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