TI MSP430 - MSP430 CPU

MSP430 CPU

The MSP430 CPU uses a von Neumann architecture, with a single address space for instructions and data. Memory is byte-addressed, and pairs of bytes are combined little-endian to make 16-bit words.

The processor contains 16 16-bit registers, of which 4 are dedicated to special purposes: R0 is the program counter, R1 is the stack pointer, R2 is the status register, and R3 is a special register called the constant generator, providing access to 6 commonly used constant values without requiring an additional operand. R3 always reads as 0 and writes to it are ignored. R4 through R15 are available for general use.

The instruction set is very simple; there are 27 instructions in three families. Most instructions are available in .B (8-bit byte) and .W (16-bit word) suffixed versions, depending on the value of a B/W bit: the bit is set to 1 for 8-bit and 0 for 16-bit. A missing suffix is equivalent to .W. Byte operations to memory affect only the addressed byte, while byte operations to registers clear the most significant byte.

MSP430 instruction set
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0	Instruction

0	0	0	1	0	0	opcode			B/W	As		register				Single-operand arithmetic
0	0	0	1	0	0	0	0	0	B/W	As		register				RRC Rotate right (1 bit) through carry
0	0	0	1	0	0	0	0	1	0	As		register				SWPB Swap bytes
0	0	0	1	0	0	0	1	0	B/W	As		register				RRA Rotate right (1 bit) arithmetic
0	0	0	1	0	0	0	1	1	0	As		register				SXT Sign extend byte to word
0	0	0	1	0	0	1	0	0	B/W	As		register				PUSH Push value onto stack
0	0	0	1	0	0	1	0	1	0	As		register				CALL Subroutine call; push PC and move source to PC
0	0	0	1	0	0	1	1	0	0	0	0	0	0	0	0	RETI Return from interrupt; pop SR then pop PC

0	0	1	condition			10-bit signed offset										Conditional jump; PC = PC + 2×offset
0	0	1	0	0	0	10-bit signed offset										JNE/JNZ Jump if not equal/zero
0	0	1	0	0	1	10-bit signed offset										JEQ/JZ Jump if equal/zero
0	0	1	0	1	0	10-bit signed offset										JNC/JLO Jump if no carry/lower
0	0	1	0	1	1	10-bit signed offset										JC/JHS Jump if carry/higher or same
0	0	1	1	0	0	10-bit signed offset										JN Jump if negative
0	0	1	1	0	1	10-bit signed offset										JGE Jump if greater or equal
0	0	1	1	1	0	10-bit signed offset										JL Jump if less
0	0	1	1	1	1	10-bit signed offset										JMP Jump (unconditionally)

opcode				source				Ad	B/W	As		destination				Two-operand arithmetic
0	1	0	0	source				Ad	B/W	As		destination				MOV Move source to destination
0	1	0	1	source				Ad	B/W	As		destination				ADD Add source to destination
0	1	1	0	source				Ad	B/W	As		destination				ADDC Add source and carry to destination
0	1	1	1	source				Ad	B/W	As		destination				SUBC Subtract source from destination (with carry)
1	0	0	0	source				Ad	B/W	As		destination				SUB Subtract source from destination
1	0	0	1	source				Ad	B/W	As		destination				CMP Compare (pretend to subtract) source from destination
1	0	1	0	source				Ad	B/W	As		destination				DADD Decimal add source to destination (with carry)
1	0	1	1	source				Ad	B/W	As		destination				BIT Test bits of source AND destination
1	1	0	0	source				Ad	B/W	As		destination				BIC Bit clear (dest &= ~src)
1	1	0	1	source				Ad	B/W	As		destination				BIS Bit set (logical OR)
1	1	1	0	source				Ad	B/W	As		destination				XOR Exclusive or source with destination
1	1	1	1	source				Ad	B/W	As		destination				AND Logical AND source with destination (dest &= src)

Instructions are 16 bits, followed by up to two 16-bit extension words. Addressing modes are specified by the 2-bit As field and the 1-bit Ad field. Some special versions can be constructed using R0, and modes other than register direct using R2 (the status register) and R3 (the constant generator) are interpreted specially. Ad can use only a subset of the addressing modes for As.

Indexed addressing modes add a 16-bit extension word to the instruction. If both source and destination are indexed, the source extension word comes first. x refers to the next extension word in the instruction stream in the table below.

MSP430 addressing modes
As	Ad	Register	Syntax	Description
00	0	n	Rn	Register direct. The operand is the contents of Rn.
01	1	n	x(Rn)	Indexed. The operand is in memory at address Rn+x.
10	—	n	@Rn	Register indirect. The operand is in memory at the address held in Rn.
11	—	n	@Rn+	Indirect autoincrement. As above, then the register is incremented by 1 or 2.

Addressing modes using R0 (PC)
01	1	0 (PC)	ADDR	Symbolic. Equivalent to x(PC). The operand is in memory at address PC+x.
11	—	0 (PC)	#x	Immediate. Equivalent to @PC+. The operand is the next word in the instruction stream.

Addressing modes using R2 (SR) and R3 (CG), special-case decoding
01	1	2 (SR)	&ADDR	Absolute. The operand is in memory at address x.
10	—	2 (SR)	#4	Constant. The operand is the constant 4.
11	—	2 (SR)	#8	Constant. The operand is the constant 8.
00	—	3 (CG)	#0	Constant. The operand is the constant 0.
01	—	3 (CG)	#1	Constant. The operand is the constant 1. There is no index word.
10	—	3 (CG)	#2	Constant. The operand is the constant 2.
11	—	3 (CG)	#−1	Constant. The operand is the constant −1.

Instructions generally take 1 cycle per word fetched or stored, so instruction times range from 1 cycle for a simple register-register instruction to 6 cycles for an instruction with both source and destination indexed.

The MSP430X extension with 20-bit addressing adds additional instructions that can require up to 10 clock cycles. Setting or clearing a peripheral bit takes two clocks. A jump, taken or not takes two clocks. With the 2xx series 2 MCLKs is 125 ns at 16 MHz.

Moves to the program counter are allowed and perform jumps. Return from subroutine, for example, is implemented as MOV @SP+,PC.

When R0 (PC) or R1 (SP) are used with the autoincrement addressing mode, they are always incremented by two. Other registers (R4 through R15) are incremented by the operand size, either 1 or 2 bytes.

The status register contains 4 arithmetic status bits, a global interrupt enable, and 4 bits that disable various clocks to enter low-power mode. When handling an interrupt, the processor saves the status register on the stack and clears the low-power bits. If the interrupt handler does not modify the saved status register, returning from the interrupt will then resume the original low-power mode.