Tejas and Jayhawk - Design and Microarchitecture

Design and Microarchitecture

Tejas would have built on the Pentium 4's NetBurst microarchitecture. Tejas was to originally be built on a 90 nm process, later moving to a 65 nm process. The 90 nm version of the processor was reported to have 1 MB L2 cache, while the 65 nm chip would increase the cache to 2 MB. There was also to be a dual core version of Tejas called Cedarmill (or Cedar Mill depending on the source). This Cedarmill should not be confused with the 65 nm Cedar Mill-based Pentium 4, which appears to be what the codename was recycled for. The trace cache capacity would likely have been increased, and the number of pipeline stages was increased to between 40 and 50 stages. There would have been an improved version of Hyper-Threading, as well as a new version of SSE, which was later backported to the Intel Core 2 series after Tejas's cancellation and named SSSE3. Tejas was slated to operate at frequencies of 7 GHz or higher, twice the clock speed of the fastest-clocked Core 2 processor, which is clocked at 3.5 GHz. However, Tejas would likely have performed worse, as it would have executed fewer instructions per clock cycle, and it would have run hotter as well with a TDP much higher than the Prescott core of Pentium 4. The CPU was cancelled late in its development after it had reached its tapeout phase.