Verification Features
The following verification features are typically not synthesizable. Instead, they assist in the creation of extensible, flexible test benches.
Read more about this topic: System Verilog
Famous quotes containing the words verification and/or features:
“A fact is a proposition of which the verification by an appeal to the primary sources of our knowledge or to experience is direct and simple. A theory, on the other hand, if true, has all the characteristics of a fact except that its verification is possible only by indirect, remote, and difficult means.”
—Chauncey Wright (1830–1875)
“All visible objects, man, are but as pasteboard masks. But in each event—in the living act, the undoubted deed—there, some unknown but still reasoning thing puts forth the mouldings of its features from behind the unreasoning mask. If man will strike, strike through the mask!”
—Herman Melville (1819–1891)