System Verilog - Interfaces

Interfaces

For small designs, the Verilog port compactly describes a module's connectivity with the surrounding environment. But major blocks within a large design hierarchy typically possess port counts in the thousands. Systemverilog introduces the interface concept, to both reduce the redundancy of port-name declarations between connected-modules, as well as group and abstract related signals into a user-declared bundle. Additional concept is modport, that shows direction of logic connections. example:

interface intf; logic a; logic b; modport in (input a, output b); modport out (input b, output a); endinterface module top; intf i ; u_a m1 (.i1(i)); u_b m2 (.i2(i)); endmodule module u_a (intf.in i1); endmodule module u_b (intf.out i2); endmodule