SDS Sigma Series - Instruction Format

Instruction Format

The format for memory-reference instructions for the 32-bit Sigma systems is as follows:

+-+--------------+--------+------+---------------------------+ |*| Op Code | R | X | Reference address | +-+--------------+--------+------+---------------------------+ bit 0 1 7 8 1 1 1 1 3 1 2 4 5 1 Bit 0 indicates indirect address. Bits 1-7 contain the operation code (opcode) Bits 8-11 encode a register operand (0:15) Bits 12-14 encode an index register (1:7). 0 indicates no indexing. Bits 16-31 encode the address of a memory word.

For the Sigma 9, when real extended addressing is enabled, the reference address field is interpreted differently depending on whether the high-order bit is 0 or 1:

+-+--------------+--------+------+-+-------------------------+ | | | | |0| Address in 1st 64K words| |*| Op Code | R | X +-+-------------------------+ | | | | |1| Low 16 bits of address | +-+--------------+--------+------+-+-------------------------+ bit 0 1 7 8 1 1 1 1 1 3 1 2 4 5 6 1

If the high-order bit is 0, the lower 16 bits of the address refer to a location in the first 64K words of main memory; if the high-order bit is 1, the lower 16 bits of the address refer to a location in a 64K-word block of memory specified by the Extension Address in bits 42-47 of the Program Status Doubleword, with the Extension Address being concatenated with the lower 16 bits of the reference address to form the physical address.