Quad Data Rate SRAM - Clocking Scheme

Clocking Scheme

• Addresses
  • Read address latched on rising edge of K
  • Write address latched on rising edge of K (in burst-of-4 mode, burst-of-2 uses rising edge of not-K)

• Data
  • Write
    • If /WPS is low
      • A data word on Data In is latched on rising edge of K
      • The next data word on Data In is latched on rising edge of /K
  • Read
    • A read is a two-cycle process
    • If /RPS is low
      • The first rising edge of K latches the read address, A
      • The second rising edge of K puts the data word, from address A, on the Data Out bus
      • The next rising edge of /K puts the next data word, from address A+1, on the Data Out bus