Power Optimization (EDA) - Power Analysis of CMOS Circuits

Power Analysis of CMOS Circuits

The power consumption of digital CMOS circuits is generally considered in terms of three components:

• The dynamic power component, related to the charging and discharging of the load capacitance at the gate output.
• The short-circuit power component. During the transition of the output line (of a CMOS gate) from one voltage level to the other, there is a period of time when both the PMOS and the NMOS transistors are on, thus creating a path from V_DD to ground.
• The static power component, due to leakage, that is present even when the circuit is not switching. This, in turn, is composed of two components - gate to source leakage, which is leakage directly though the gate insulator, mostly by tunnelling, and source-drain leakage attributed to both tunnelling and sub-threshold conduction. The contribution of the static power component to the total power number is growing very rapidly in the current era of Deep Sub-Micrometre (DSM) Design.

Power can be estimated at a number of levels of detail. The higher levels of abstraction are faster and handle larger circuits, but are less accurate. The main levels include:

• Circuit Level Power Estimation, using a circuit simulator such as SPICE
• Static Power Estimation does not use the input vectors, but may use the input statistics. Analogous to static timing analysis.
• Logic-Level Power Estimation, often linked to logic simulation.
• Analysis at the Register-Transfer Level. Fast and high capacity, but not as accurate.