Power Optimization (EDA) - Circuit-level Power Optimization

Circuit-level Power Optimization

Many different techniques are used to reduce power consumption at the circuit level. Some of the main ones are:

• Transistor sizing: adjusting the size of each gate or transistor for minimum power.
• Voltage scaling: lower supply voltages use less power, but go slower.
• Voltage islands: Different blocks can be run at different voltages, saving power. This design practice may require the use of level-shifters when two blocks with different supply voltages communicate with each other.
• Variable V_DD: The voltage for a single block can be varied during operation - high voltage (and high power) when the block needs to go fast, low voltage when slow operation is acceptable.
• Multiple threshold voltages: Modern processes can build transistors with different thresholds. Power can be saved by using a mixture of CMOS transistors with two or more different threshold voltages. In the simplest form there are two different thresholds available, common called High-Vt and Low-Vt, where Vt stands for threshold voltage. High threshold transistors are slower but leak less, and can be used in non-critical circuits.
• Power gating: This technique uses high Vt sleep transistors which cut-off a circuit block when the block is not switching. The sleep transistor sizing is an important design parameter. This technique, also known as MTCMOS, or Multi-Threshold CMOS reduces stand-by or leakage power, and also enables Iddq testing.
• Long-Channel transistors: Transistors of more than minimum length leak less, but are bigger and slower.
• Stacking and parking states: Logic gates may leak differently during logically equivalent input states (say 10 on a NAND gate, as opposed to 01). State machines may have less leakage in certain states.
• Logic styles: dynamic and static logic, for example, have different speed/power tradeoffs.