POWER2+
An improved version of the POWER2 optimized for transaction processing was introduced in May 1994 as the POWER2+. Transaction processing workloads benefited from the addition of a L2 cache with capacities of 512 KB, 1 MB and 2 MB. This cache was implemented off-package with industry-standard burst SRAMs. The cache was connected to the POWER2+ via a 64- (for low-end systems) or 128-bit bus (for high-end systems). The cache was direct-mapped, had a 128-byte line size, and was write-through. The cache tags were contained on the storage control unit chip. The POWER2+ has a narrower 64- or 128-bit memory bus and a smaller 64 or 128 KB data cache. As there is less cache, the data cache unit chips are smaller as a result, and the revised storage control unit chip is also smaller. A goal for the six-chip configuration was to reduce cost, and therefore the chips are packaged in a solder ball connect (SBC) package instead of a MCM.
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