Introduction
In a processor-based system, the speed of the processor is always more than that of the main memory. As a result unnecessary wait-states are developed when instructions or data are being fetched from the main memory. This causes a hampering of the performance of the system. A cache memory is basically developed to increase the efficiency of the system and to maximise the utilisation of the entire computational speed of the processor.
The performance of the processor is highly influenced by the methods employed to transfer data and instructions to and from the processor.The less the time needed for the transfers the better the processor performance.
The Pipeline Burst Cache is basically a storage area for a processor that is designed to be read from or written to in a pipelined succession of four data transfers. As the name suggests 'pipelining', the transfers after the first transfer happen before the first transfer has arrived at the processor. It was developed as an alternative to asynchronous cache and synchronous burst cache.
It was first implemented in the year 1996 by Intel in the Pentium microprocessor.
Read more about this topic: Pipeline Burst Cache
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