Multi-core DSP
Picochip developed a multi-core digital signal processor, the picoArray. This integrates 250-300 individual DSP cores onto a single die (depending on the specific product). Each of these cores is a 16-bit processor with Harvard architecture, local memory and 3-way VLIW.
The company has three multi-core DSP products currently available (PC202 / 203 / 205) which deliver approximately 40 GMACS and 200 GIPS of performance. The earlier PC102 is obsolete.
The programming model allows each processor to be coded independently (in ANSI C or assembler) and then to communicate over an any:any interconnect mesh. The communication flows are fixed at compile time, not dynamically at run time (analogous to place & route of an FPGA but at higher level of abstraction). This can be described as communicating sequential processes. Each process maps to a processor, which is fully independent from other processors with "encapsulation", with interaction only through defined message passing and data flows through the mesh. This architecture is also related to object-oriented programming concepts. Notably, the development environment is deterministic: simulation of code is cycle-accurate to hardware execution. Advantages claimed include ease of development, improved reliability of code and software-reuse.
Although the picoArray architecture is generic and could in principle be used for any DSP application, the company has stated its strategy is to focus on wireless infrastructure. In particular, the processor is widely used for baseband processing in WiMAX base stations and for femtocells.
Independent benchmarks of representative communications systems by Berkeley Design (BDTI) indicate that the picoArray delivers significantly better performance-per-dollar than traditional single-core DSP devices.
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