Pico Blaze - Architectural Notes

Architectural Notes

Xilinx documents the PicoBlaze as requiring just 96 FPGA slices. The small implementation size is achieved in part through a fairly rigid separation of the instruction sequencing side (program counter, call-return stack, implied stack pointer, and interrupt enable bit) from the execution side (ALU, register file, scratchpad RAM, Z/C status bits). The only information which flows from the compute side to the sequencing side are the zero and carry ALU status bits, when tested by the conditional JUMP and CALL instructions. It is not possible to implement computed jumps or function pointers. The only information which flows from the sequencing side to the execution side are operand fields: destination register (4 bits), ALU opcode (six bits), optional source register (4 bits), optional 8-bit immediate value/port-address, optional 6-bit scratchpad address. There is no mechanism to inspect the value of the stack pointer, the contents of the 31-entry stack, the interrupt enable bit, or the contents of program memory.

The instruction sequencing side does not contain an adder, so relative branches and position independent code are not possible. All jump and call addresses are absolute.

The PicoBlaze is poorly suited to programming in compiled languages such as C. In addition to the lack of support for function pointers, there are no instructions or addressing modes to expedite a stack-based calling convention. For PicoBlaze it takes two instructions to implement PUSH or POP and two instructions to implement relative addressing off a software-designated stack pointer. The PicoBlaze is better suited to a hand-optimized register-based calling convention. This does not preclude the use of a Forth-like data stack, and in fact the PicoBlaze is well suited to this approach, if the 64-byte scratchpad memory offers sufficient space.