Physical verification is a process whereby an IC layout design is checked via EDA software tools to see if it meets certain criteria. Verification involves DRC (Design rule check), LVS (Layout versus schematic), ERC (Electrical Rule Check), XOR (Exclusive OR), and Antenna Checks.
Read more about Physical Verification: XOR Check, Antenna Check, ERC (Electrical Rule Check)
Famous quotes containing the words physical and/or verification:
“Man’s characteristic privilege is that the bond he accepts is not physical but moral; that is, social. He is governed not by a material environment brutally imposed on him, but by a conscience superior to his own, the superiority of which he feels. Because the greater, better part of his existence transcends the body, he escapes the body’s yoke, but is subject to that of society.”
—Emile Durkheim (1858–1917)
“A fact is a proposition of which the verification by an appeal to the primary sources of our knowledge or to experience is direct and simple. A theory, on the other hand, if true, has all the characteristics of a fact except that its verification is possible only by indirect, remote, and difficult means.”
—Chauncey Wright (1830–1875)