Parallel Random-access Machine - Example Code

Example Code

This is an example of SystemVerilog code which finds the maximum value in the array in only 2 clock cycles. It compares all the combinations of the elements in the array at the first clock, and merges the result at the second clock. It uses CRCW memory; m <= 1 and maxNo <= data are written concurrently. The concurrency causes no conflicts because the algorithm guarantees that the same value is written to the same memory. This code can be run on FPGA hardware.

module FindMax #(parameter int len = 8) (input bit clock, resetN, input bit data, output bit maxNo); typedef enum bit {COMPARE, MERGE, DONE} State; State state; bit m; int i, j; always_ff @(posedge clock, negedge resetN) begin if (!resetN) begin for (i = 0; i < len; i++) m <= 0; state <= COMPARE; end else begin case (state) COMPARE: begin for (i = 0; i < len; i++) begin for (j = 0; j < len; j++) begin if (data < data) m <= 1; end end state <= MERGE; end MERGE: begin for (i = 0; i < len; i++) begin if (m == 0) maxNo <= data; end state <= DONE; end endcase end end endmodule

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