Operation
In traditional 32-bit protected mode, x86 processors use a two-level page translation scheme, where the control register CR3 points to a single 4 KiB long page directory, which is divided into 1024 x 4 byte entries that point to 4 KiB long page tables, similarly consisting of 1024 x 4 byte entries pointing to 4 KiB long pages.
Enabling PSE (by setting bit 4, PSE, of the system register CR4) changes this scheme. The entries in the page directory have an additional flag, in bit 7, named PS (for Page Size). This flag was ignored without PSE, but now, the page directory entry with PS set to 1 does not point to a page table, but to a single large 4 MiB page. The page directory entry with PS set to 0 behaves as without PSE.
Read more about this topic: Page Size Extension
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—Marshall McLuhan (1911–1980)
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