Instruction Structure
NAR 2 processor Machine instructions was made of a single 32-bit machine word and contained:
- opcode in 8 most significant bits (bits 24 to 31)
- 4 bits (20 to 23) specifying the Index register to use with indexed addressing modes
- 4 bits (16 to 19) containing address mode flags:
- bit 19: P (sr. Posredno, en. mediated) - indexed
- bit 18: R (sr. Relativno) - relative to program counter
- bit 17: I (sr. Indirektno) - multi-level memory indirect (note: the address is loaded from specified location and, should it also specify "I" flag the indirect address calculation continues)
- bit 16: N (sr. Neposredno) - immediate
- 16 bit signed parameter value
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