NAR 2 - Addressing Modes

Addressing Modes

With four address mode selection bits (P, R, I and N - indexed, relative, indirect and immediate), NAR 2 instructions can specify 16 different addressing modes but not all make sense in all instructions. In the following table:

  • M specifies the 32-bit value (content) of memory location x
  • BN specifies the program counter
  • p specifies the 16-bit signed parameter at location
  • Xi specifies the index register selected by data at location
  • f is the "effective value" function used for indirect addressing (see details below):
Addr. flags Instruction type
P R I N Data Jump
- - - - M p
- - - N p p
- - I - M)] f(M)
- - I N f(M) f(M)
- R - - M BN+p
- R - N BN+p BN+p
- R I - M)] f(M)
- R I N f(M) f(M)
P - - - M Xi+p
P - - N Xi+p Xi+p
P - I - M)] f(M)
P - I N f(M) f(M)
P R - - M BN+Xi+p
P R - N BN+Xi+p BN+Xi+p
P R I - M)] f(M)
P R I N f(M) f(M)

Note 1: "N" (immediate) flag has no effect on jump (flow control) instructions, as the processor can not jump into a specified value, but only to a memory address.

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