Specifications
NAR 1 processor has a 5-bit address bus (32 bytes of addressable memory) and 8-bit data bus. Machine instructions were single-byte with three most significant bits specifying the opcode and 5 least significant bits the parameter - memory address. A single 8-bit accumulator register was available and there were no flags or flag registers. Only absolute addressing mode was available and all others were achieved by self-modifying code.
Even though this is only a theoretical computer the following physical characteristics were given:
- Memory cycle: 1μs
- Arithmetic operation (SABF) cycle: 0.9μs (900ns)
- Control panel facilitates power on and off, memory data entry and readout, instruction counter entry and selection of either program execution mode or control panel mode.
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